1. Field of the Invention
The present invention relates to a method of manufacturing a complementary metal oxide semiconductor (CMOS) device, and more particularly, to a method of manufacturing a CMOS device with selective epitaxial growth (SEG) and metal gate.
2. Description of the Prior Art
As semiconductor processes advance to very deep sub-micron geometries and with the progress of device miniaturization, enhancing carrier mobility and driving current of a MOS transistor has become a critical issue. For example, manufacturing source/drain of a MOS transistor with selective epitaxial growth (SEG) technology is used to improve electrical performance of those elements.
Please refer to FIGS. 1-3, which are schematic drawings illustrating a conventional method of manufacturing a CMOS device. As shown in FIG. 1, a substrate 100 comprising an N-type well 102, a P-type well 104 and shallow trench isolations (STIs) 106 formed in between is provided. Gate structures 112 and 114 are respectively formed on the N-type well 102 and the P-type well 104 by etching a polysilicon layer 110 and a dielectric layer with a patterned SiN hard mask layer 108 serving as an etching mask. Then, a seal layer 120 is formed and followed by forming P-type lightly doped drains (P-LDDs) 122 and N-type LDDs (N-LDDs) 124 respectively in the N-type well 102 and the P-type well 104. After forming the P-LDDs 122 and N-LDDs 124, a SiN layer 130 is formed on the substrate 100.
Please refer to FIG. 2. The seal layer 120 and the SiN layer 130 are then patterned to form a SiN protecting layer 130a covering the P-type well 104 and a SiN first spacer 132 at sidewall of the gate structure 112. The SiN protecting layer 130a and the SiN first spacer 132 serve as an etching mask in a following etching process used to form recesses (not shown) respectively at two sides of the gate structure 112 in the N-type well 102. A selective epitaxial growth (SEG) process is performed to form epitaxial silicon layers 140 respectively in each recess. As shown in FIG. 2, it is noteworthy that while the SiN hard mask layer 108 covering the polysilicon layer 110 of the gate structure 112 is getting thinner due to consumption in the etching process, the hard mask layer 108 covering the polysilicon layer 110 of the gate structure 114 is protected from the consumption by the SiN protecting layer 130a. Consequently, there will be a height deviation A that is more than 250 angstroms (Å) between the hard mask layer 108 covering the gate structure 112 and the hard mask layer 108 covering the gate structure 114.
Please refer to FIG. 3. It is well-known to those skilled in the art that after forming the epitaxial silicon layer 140, a second spacer 150 is formed by sequentially forming an insulating layer (not shown) on the substrate 200 and etching the insulating layer, the SiN protecting layer 130a, and the first spacer 132. Thus the second spacer 150 is formed on the sidewalls of the gate structures 112 and 114. Then, sequentially forming a P-type source/drain 152 in the epitaxial silicon layer 140 and an N-type source/drain 154 in the substrate 100 at two sides of the gate structure 114. As shown in FIG. 3, because the second spacer 150 is formed after forming the epitaxial silicon layer 140, the second spacer 150 is to cover a portion of the epitaxial silicon layer 140. Then, a self-aligned silicide (salicide) process is performed to form salicide layers (not shown) on the P-type and N-type source/drains 152 and 154. Thus, a PMOS transistor 162 and an NMOS transistor 164 are obtained. After forming the salicide layers, an interlayer dielectric (ILD) layer (not shown) is formed to cover the PMOS and NMOS transistors 162 and 164.
In addition, since the conventional polysilicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices, metal gate approach is introduced to be the control electrode. Accordingly, a chemical-mechanical polishing (CMP) process is performed to remove the unnecessary ILD layer and the hard mask 108. Therefore the polysilicon layers 110 are following removed for forming metal gates that are used to replace the conventional polysilicon gate.
Please still refer to FIG. 3. It is noteworthy that the size of the second spacer 150 of the NMOS transistor 164 is larger than that of the PMOS transistor 162. Furthermore, a serious bottom footing defect as shown in circle B designated in FIG. 3 is always found in the second spacer 150 of the NMOS transistor 164 due to the height deviation A between the two gate structures 112 and 114. Such footing defect further adversely impacts profiles of the following formed N-type source/drain 154. Moreover, since the footing defect occupies a portion of the valuable surface of the source/drain 154, it is impossible to form the salicide layer on the surface covered by the second spacer 150. As the critical dimension (CD) keeps shrinking, the salicide layer missed on the surface of the source/drain 154 leads to an undesired raise of contact resistance (Rc). The height deviation A also causes adverse affect such as a seam obtained in the NMOS transistor 164 during forming the ILD layer, and complicates process control during performing the CMP process.
Therefore, a method of manufacturing a CMOS device is still needed to overcome the abovementioned problems.